www.siliconstandard.com 1 of 6 SSM40N03S n-channel enhancement-mode power mosfet low gate charge bv dss 30v simple drive requirement r ds(on) 17m fast switching i d 40a description absolute maximum ratings symbol units v ds v v gs v i d @t c =25 a i d @t c =100 a i dm a p d @t c =25 w w/ t stg t j symbol value unit rthj-c thermal resistance junction-case max. 2.5 /w rthj-a thermal resistance junction-ambient max. 62 /w parameter rating drain-source voltage 30 gate-source voltage continuous drain current, v gs @ 10v 40 continuous drain current, v gs @ 10v 30 pulsed drain current 1 169 total power dissipation 50 -55 to 150 operating junction temperature range -55 to 150 linear derating factor 0.4 thermal data parameter storage temperature range power mosfets from silicon standard corp. provide the designer with the best combination of fast switching, ruggedized device design, low on-resistance and cost-effectiveness. the to-263 package is widely preferred for all commercial and industrial surface mount applications and suited for low voltage applications such as dc/dc converters. the through-hole version ( ssm40n03p) is available for low-footprint applications. 20 g d s to-263 g d s re v . 2.01 6/26/2003
www.siliconstandard.com 2 of 6 SSM40N03S electrical characteristics @ t j =25 o c (unless otherwise specified) symbol parameter test conditions min. typ. max. units bv dss drain-source breakdown voltage v gs =0v, i d =250ua 30 - - v $ b v dss / $ t j breakdown voltage temperature coefficient reference to 25 # , i d =1ma - 0.037 -v/ # r ds(on) static drain-source on-resistance v gs =10v, i d =20a - 14 17 m " v gs =4.5v, i d =16a - 20 23 m " v gs(th) gate threshold voltage v ds =v gs , i d =250ua 1 - 3 v g fs forward transconductance v ds =10v, i d =20a - 26 - s i dss drain-source leakage current (t j =25 o c) v ds =30v, v gs =0v - - 1 ua drain-source leakage current (t j =150 o c) v ds =24v, v gs =0v - - 25 ua i gss gate-source forward leakage v gs =-- na q g total gate charge 2 i d =20a - 17 - nc q gs gate-source charge v ds =24v - 3 - nc q gd gate-drain ("miller") charge v gs =5v - 10 - nc t d(on) turn-on delay time 2 v ds =15v - 7.2 - ns t r rise time i d =20a - 60 - ns t d(off) turn-off delay time r g =3.3 " , v gs =10v - 22.5 - ns t f fall time r d =0.75 " -10- ns c iss input capacitance v gs =0v - 800 - pf c oss output capacitance v ds =25v - 380 - pf c rss reverse transfer capacitance f=1.0mhz - 133 - pf source-drain diode symbol parameter test conditions min. typ. max. units i s continuous source current ( body diode ) v d =v g =0v , v s =1.3v - - 40 a i sm pulsed source current ( body diode ) 1 - - 169 a v sd forward on voltage 2 t j =25 # , i s =40a, v gs =0v - - 1.3 v notes: 1.pulse width limited by safe operating area. 2.pulse width < 300us , duty cycle < 2%. 20v 100 re v . 2.01 6/26/2003
www.siliconstandard.com 3 of 6 SSM40N03S fig 1. typical output characteristics fig 2. typical output characteristics fig 3. on-resistance v.s. gate voltage fig 4. normalized on-resistance v.s. junction temperature 0.60 0.80 1.00 1.20 1.40 1.60 1.80 -50 0 50 100 150 t j , junction temperature ( o c) normalized r ds(on) v g =10v i d =20a 0 50 100 150 0123456789 v ds , drain-to-source voltage (v) i d , drain current (a) t c =25 o c v g =3.0v v g =4.0v v g =6.0v v g =8.0v v g =10v 0 50 100 150 012345678910 v ds , drain-to-source voltage (v) i d , drain current (a) t c =150 o c v g =6.0v v g =3.0v v g =4.0v v g =8.0v v g =10v 12 14 16 18 20 22 24 26 28 34567891011 v gs (v) r dson (m ) i d =20a t c =25 o c re v . 2.01 6/26/2003
www.siliconstandard.com 4 of 6 SSM40N03S fig 5. maximum drain current v.s. fig 6. typical power dissipation case temperature fig 7. maximum safe operating area fig 8. effective transient thermal impedance 0 5 10 15 20 25 30 35 40 45 50 25 50 75 100 125 150 t c , case temperature ( o c) i d , drain current (a) 0 10 20 30 40 50 60 0 50 100 150 t c ,case temperature ( o c) p d (w) 1 10 100 1000 1 10 100 v ds (v) i d (a) t c =25 o c single pulse 10us 100us 1ms 10ms 100ms 0.01 0.1 1 0.00001 0.0001 0.001 0.01 0.1 1 t , pulse width (s) normalized thermal response (r thjc ) p dm duty factor = t/t peak t j = p dm x r thjc + t c t t 0.02 0.01 0.05 0.1 0.2 duty=0.5 single pulse re v . 2.01 6/26/2003
www.siliconstandard.com 5 of 6 SSM40N03S fig 9. gate charge characteristics fig 10. typical capacitance characteristics fig 11. forward characteristic of fig 12. gate threshold voltage v.s. reverse diode junction temperature 0 1 2 3 -50 0 50 100 150 t j , junction temperature ( o c) v gs(th) (v) 0 2 4 6 8 10 12 14 16 0 5 10 15 20 25 30 35 40 q g , total gate charge (nc) v gs , gate to source voltage (v) v d =24v v d =20v v d =16v i d=20a 0.01 0.1 1 10 100 0.1 0.3 0.5 0.7 0.9 1.1 1.3 1.5 v sd (v) i s (a) t j = 25 o c t j = 150 o c 100 1000 10000 1 5 9 1317212529 v ds (v) c (pf) f =1.0mhz ciss coss crss re v . 2.01 6/26/2003
www.siliconstandard.com 6 of 6 in formation furnished by silicon standard corporation is believed to be accurate and reliable. however, silicon standard corporation makes no guarantee or warranty, expre ss or implied, as to the reliability, accuracy, timeliness or completeness of such information and assumes no responsibility for its use, or for infringement of any patent or other intellectual property rights of third parties that may result from its use. silicon standard reserves the right to make changes as it deems necessary to any products described herein for any reason, including without limitation enhancement in reliability, functionality or design. no license is granted, whether expressly or by i m plication, in relation to the use of any products described herein or to the use of any information provided herein, under any patent or other intellectual property rights of silicon standard corporation or any third parties. SSM40N03S fig 13. switching time circuit fig 14. switching time waveform fig 15. gate charge circuit fig 16. gate charge waveform t d(on) t r t d(off) t f v ds v gs 10% 90% q v g 5v q gs q gd q g charge 0.5x rated v ds to the oscilloscope - + 10 v d g s v ds v gs r g r d 0.8 x rated v ds to the oscilloscope - + d g s v ds v gs i d i g 1~3 m a re v . 2.01 6/26/2003
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